2021-11-15 07:03:24 +01:00
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// Copyright (c) 2018 Cirque Corp. Restrictions apply. See: www.cirque.com/sw-license
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#include "cirque_pinnacle.h"
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#include "spi_master.h"
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// Masks for Cirque Register Access Protocol (RAP)
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#define WRITE_MASK 0x80
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#define READ_MASK 0xA0
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2022-05-13 08:21:25 +02:00
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#define FILLER_BYTE 0xFC
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2021-11-15 07:03:24 +01:00
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extern bool touchpad_init;
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/* RAP Functions */
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// Reads <count> Pinnacle registers starting at <address>
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void RAP_ReadBytes(uint8_t address, uint8_t* data, uint8_t count) {
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2022-02-12 19:29:31 +01:00
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uint8_t cmdByte = READ_MASK | address; // Form the READ command byte
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2021-11-15 07:03:24 +01:00
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if (touchpad_init) {
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2021-12-15 22:41:07 +01:00
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if (spi_start(CIRQUE_PINNACLE_SPI_CS_PIN, CIRQUE_PINNACLE_SPI_LSBFIRST, CIRQUE_PINNACLE_SPI_MODE, CIRQUE_PINNACLE_SPI_DIVISOR)) {
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2022-05-13 08:21:25 +02:00
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spi_write(cmdByte); // write command byte, receive filler
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spi_write(FILLER_BYTE); // write & receive filler
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spi_write(FILLER_BYTE); // write & receive filler
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2021-11-15 07:03:24 +01:00
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for (uint8_t i = 0; i < count; i++) {
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2022-05-13 08:21:25 +02:00
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data[i] = spi_write(FILLER_BYTE); // write filler, receive data on the third filler send
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2021-11-15 07:03:24 +01:00
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}
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} else {
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2022-08-29 19:16:49 +02:00
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pd_dprintf("error cirque_pinnacle spi_start read\n");
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2021-11-15 07:03:24 +01:00
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touchpad_init = false;
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}
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spi_stop();
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}
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}
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// Writes single-byte <data> to <address>
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void RAP_Write(uint8_t address, uint8_t data) {
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2022-02-12 19:29:31 +01:00
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uint8_t cmdByte = WRITE_MASK | address; // Form the WRITE command byte
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2021-11-15 07:03:24 +01:00
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if (touchpad_init) {
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2021-12-15 22:41:07 +01:00
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if (spi_start(CIRQUE_PINNACLE_SPI_CS_PIN, CIRQUE_PINNACLE_SPI_LSBFIRST, CIRQUE_PINNACLE_SPI_MODE, CIRQUE_PINNACLE_SPI_DIVISOR)) {
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2021-11-15 07:03:24 +01:00
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spi_write(cmdByte);
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spi_write(data);
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} else {
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2022-08-29 19:16:49 +02:00
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pd_dprintf("error cirque_pinnacle spi_start write\n");
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2021-11-15 07:03:24 +01:00
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touchpad_init = false;
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}
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spi_stop();
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}
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}
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