Cipulot
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636c96ad25
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Add EC Virgo (#23173)
Co-authored-by: jack <0x6a73@protonmail.com>
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2024-04-30 18:34:37 +01:00 |
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Cipulot
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ed791972e1
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Cipulot refactoring (#22368)
Co-authored-by: Drashna Jaelre <drashna@live.com>
Co-authored-by: Joel Challis <git@zvecr.com>
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2024-02-26 13:05:10 +11:00 |
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Duncan Sutherland
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ebec17adea
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Add 'JIS' form factor layouts (#21220)
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2023-07-08 00:36:34 +10:00 |
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Ryan
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ef6a712899
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Even more info.json whitespace cleanups (#20703)
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2023-05-04 19:09:59 +10:00 |
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Ryan
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47966dc2a6
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Migrate rgblight.pin and RGB_DI_PIN to ws2812.pin (#20303)
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2023-04-06 18:00:54 +10:00 |
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Ryan
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d8aec71e48
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Remove trailing zeroes in info.json layouts (#20156)
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2023-03-17 14:21:53 +00:00 |
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Cipulot
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4283e69ac7
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RF R1 8-9Xu PCB (#20048)
Co-authored-by: Tom Barnes <barnestom@me.com>
Co-authored-by: Drashna Jaelre <drashna@live.com>
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2023-03-14 07:41:06 +00:00 |
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