8e614250b4
Co-authored-by: Pablo Martínez <58857054+elpekenin@users.noreply.github.com> Co-authored-by: Dasky <32983009+daskygit@users.noreply.github.com> Fixup delta frame coordinates after #20296.
132 lines
6 KiB
C
132 lines
6 KiB
C
// Copyright 2021-2023 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "qp_internal.h"
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#include "qp_comms.h"
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#include "qp_ssd1351.h"
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#include "qp_ssd1351_opcodes.h"
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#include "qp_tft_panel.h"
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#ifdef QUANTUM_PAINTER_SSD1351_SPI_ENABLE
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# include "qp_comms_spi.h"
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#endif // QUANTUM_PAINTER_SSD1351_SPI_ENABLE
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Common
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// Driver storage
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tft_panel_dc_reset_painter_device_t ssd1351_drivers[SSD1351_NUM_DEVICES] = {0};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Initialization
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__attribute__((weak)) bool qp_ssd1351_init(painter_device_t device, painter_rotation_t rotation) {
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tft_panel_dc_reset_painter_device_t *driver = (tft_panel_dc_reset_painter_device_t *)device;
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// clang-format off
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const uint8_t ssd1351_init_sequence[] = {
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// Command, Delay, N, Data[N]
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SSD1351_COMMANDLOCK, 5, 1, 0x12,
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SSD1351_COMMANDLOCK, 5, 1, 0xB1,
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SSD1351_DISPLAYOFF, 5, 0,
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SSD1351_CLOCKDIV, 5, 1, 0xF1,
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SSD1351_MUXRATIO, 5, 1, 0x7F,
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SSD1351_DISPLAYOFFSET, 5, 1, 0x00,
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SSD1351_SETGPIO, 5, 1, 0x00,
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SSD1351_FUNCTIONSELECT, 5, 1, 0x01,
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SSD1351_PRECHARGE, 5, 1, 0x32,
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SSD1351_VCOMH, 5, 1, 0x05,
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SSD1351_NORMALDISPLAY, 5, 0,
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SSD1351_CONTRASTABC, 5, 3, 0xC8, 0x80, 0xC8,
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SSD1351_CONTRASTMASTER, 5, 1, 0x0F,
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SSD1351_SETVSL, 5, 3, 0xA0, 0xB5, 0x55,
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SSD1351_PRECHARGE2, 5, 1, 0x01,
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SSD1351_DISPLAYON, 5, 0,
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};
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// clang-format on
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qp_comms_bulk_command_sequence(device, ssd1351_init_sequence, sizeof(ssd1351_init_sequence));
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// Configure the rotation (i.e. the ordering and direction of memory writes in GRAM)
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const uint8_t madctl[] = {
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[QP_ROTATION_0] = SSD1351_MADCTL_BGR | SSD1351_MADCTL_MY,
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[QP_ROTATION_90] = SSD1351_MADCTL_BGR | SSD1351_MADCTL_MX | SSD1351_MADCTL_MY | SSD1351_MADCTL_MV,
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[QP_ROTATION_180] = SSD1351_MADCTL_BGR | SSD1351_MADCTL_MX,
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[QP_ROTATION_270] = SSD1351_MADCTL_BGR | SSD1351_MADCTL_MV,
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};
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qp_comms_command_databyte(device, SSD1351_SETREMAP, madctl[rotation]);
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qp_comms_command_databyte(device, SSD1351_STARTLINE, (rotation == QP_ROTATION_0 || rotation == QP_ROTATION_90) ? driver->base.panel_height : 0);
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return true;
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Driver vtable
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const tft_panel_dc_reset_painter_driver_vtable_t ssd1351_driver_vtable = {
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.base =
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{
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.init = qp_ssd1351_init,
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.power = qp_tft_panel_power,
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.clear = qp_tft_panel_clear,
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.flush = qp_tft_panel_flush,
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.pixdata = qp_tft_panel_pixdata,
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.viewport = qp_tft_panel_viewport,
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.palette_convert = qp_tft_panel_palette_convert_rgb565_swapped,
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.append_pixels = qp_tft_panel_append_pixels_rgb565,
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.append_pixdata = qp_tft_panel_append_pixdata,
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},
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.num_window_bytes = 1,
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.swap_window_coords = true,
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.opcodes =
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{
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.display_on = SSD1351_DISPLAYON,
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.display_off = SSD1351_DISPLAYOFF,
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.set_column_address = SSD1351_SETCOLUMN,
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.set_row_address = SSD1351_SETROW,
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.enable_writes = SSD1351_WRITERAM,
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},
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// SPI
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#ifdef QUANTUM_PAINTER_SSD1351_SPI_ENABLE
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// Factory function for creating a handle to the SSD1351 device
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painter_device_t qp_ssd1351_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode) {
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for (uint32_t i = 0; i < SSD1351_NUM_DEVICES; ++i) {
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tft_panel_dc_reset_painter_device_t *driver = &ssd1351_drivers[i];
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if (!driver->base.driver_vtable) {
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driver->base.driver_vtable = (const painter_driver_vtable_t *)&ssd1351_driver_vtable;
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driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
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driver->base.panel_width = panel_width;
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driver->base.panel_height = panel_height;
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driver->base.rotation = QP_ROTATION_0;
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driver->base.offset_x = 0;
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driver->base.offset_y = 0;
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driver->base.native_bits_per_pixel = 16; // RGB565
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// SPI and other pin configuration
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driver->base.comms_config = &driver->spi_dc_reset_config;
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driver->spi_dc_reset_config.spi_config.chip_select_pin = chip_select_pin;
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driver->spi_dc_reset_config.spi_config.divisor = spi_divisor;
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driver->spi_dc_reset_config.spi_config.lsb_first = false;
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driver->spi_dc_reset_config.spi_config.mode = spi_mode;
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driver->spi_dc_reset_config.dc_pin = dc_pin;
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driver->spi_dc_reset_config.reset_pin = reset_pin;
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driver->spi_dc_reset_config.command_params_uses_command_pin = false;
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if (!qp_internal_register_device((painter_device_t)driver)) {
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memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
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return NULL;
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}
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return (painter_device_t)driver;
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}
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}
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return NULL;
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}
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#endif // QUANTUM_PAINTER_SSD1351_SPI_ENABLE
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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