122 lines
4.3 KiB
C
122 lines
4.3 KiB
C
/* Copyright 2021 QMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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/* GD32VF103 has the same API as STM32F103, but uses different names for literally the same thing.
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* As of 23.7.2021 QMK is tailored to use STM32 defines/names, for compatibility sake
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* we just redefine the GD32 names. */
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/* Close your eyes kids. */
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#define MCU_STM32
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/* AFIO redefines */
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#define MAPR PCF0
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#define AFIO_MAPR_USART1_REMAP AFIO_PCF0_USART0_REMAP
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#define AFIO_MAPR_USART2_REMAP AFIO_PCF0_USART1_REMAP
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#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_PCF0_USART2_REMAP_PARTIALREMAP
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#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_PCF0_USART2_REMAP_FULLREMAP
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/* DMA redefines. */
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#define STM32_DMA_STREAM(stream) GD32_DMA_STREAM(stream)
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#define STM32_DMA_STREAM_ID(peripheral, channel) GD32_DMA_STREAM_ID(peripheral - 1, channel - 1)
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#define STM32_DMA_CR_DIR_M2P GD32_DMA_CTL_DIR_M2P
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#define STM32_DMA_CR_PSIZE_WORD GD32_DMA_CTL_PWIDTH_WORD
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#define STM32_DMA_CR_PSIZE_HWORD GD32_DMA_CTL_PWIDTH_HWORD
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#define STM32_DMA_CR_MSIZE_WORD GD32_DMA_CTL_MWIDTH_WORD
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#define STM32_DMA_CR_MSIZE_BYTE GD32_DMA_CTL_MWIDTH_BYTE
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#define STM32_DMA_CR_MINC GD32_DMA_CTL_MNAGA
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#define STM32_DMA_CR_CIRC GD32_DMA_CTL_CMEN
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#define STM32_DMA_CR_PL GD32_DMA_CTL_PRIO
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#define STM32_DMA_CR_CHSEL GD32_DMA_CTL_CHSEL
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#define cr1 ctl0
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#define cr2 ctl1
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#define cr3 ctl2
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#define dier dmainten
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/* ADC redefines */
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#if HAL_USE_ADC
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# define STM32_ADC_USE_ADC1 GD32_ADC_USE_ADC0
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# define smpr1 sampt0
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# define smpr2 sampt1
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# define sqr1 rsq0
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# define sqr2 rsq1
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# define sqr3 rsq2
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# define ADC_SMPR2_SMP_AN0 ADC_SAMPT1_SMP_SPT0
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# define ADC_SMPR2_SMP_AN1 ADC_SAMPT1_SMP_SPT1
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# define ADC_SMPR2_SMP_AN2 ADC_SAMPT1_SMP_SPT2
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# define ADC_SMPR2_SMP_AN3 ADC_SAMPT1_SMP_SPT3
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# define ADC_SMPR2_SMP_AN4 ADC_SAMPT1_SMP_SPT4
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# define ADC_SMPR2_SMP_AN5 ADC_SAMPT1_SMP_SPT5
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# define ADC_SMPR2_SMP_AN6 ADC_SAMPT1_SMP_SPT6
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# define ADC_SMPR2_SMP_AN7 ADC_SAMPT1_SMP_SPT7
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# define ADC_SMPR2_SMP_AN8 ADC_SAMPT1_SMP_SPT8
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# define ADC_SMPR2_SMP_AN9 ADC_SAMPT1_SMP_SPT9
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# define ADC_SMPR1_SMP_AN10 ADC_SAMPT0_SMP_SPT10
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# define ADC_SMPR1_SMP_AN11 ADC_SAMPT0_SMP_SPT11
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# define ADC_SMPR1_SMP_AN12 ADC_SAMPT0_SMP_SPT12
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# define ADC_SMPR1_SMP_AN13 ADC_SAMPT0_SMP_SPT13
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# define ADC_SMPR1_SMP_AN14 ADC_SAMPT0_SMP_SPT14
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# define ADC_SMPR1_SMP_AN15 ADC_SAMPT0_SMP_SPT15
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# define ADC_SQR3_SQ1_N ADC_RSQ2_RSQ1_N
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#endif
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/* FLASH redefines */
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#if defined(EEPROM_ENABLE)
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# define SR STAT
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# define FLASH_SR_BSY FLASH_STAT_BUSY
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# define FLASH_SR_PGERR FLASH_STAT_PGERR
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# define FLASH_SR_EOP FLASH_STAT_ENDF
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# define FLASH_SR_WRPRTERR FLASH_STAT_WPERR
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# define FLASH_SR_WRPERR FLASH_SR_WRPRTERR
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# define FLASH_OBR_OPTERR FLASH_OBSTAT_OBERR
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# define AR ADDR
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# define CR CTL
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# define FLASH_CR_PER FLASH_CTL_PER
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# define FLASH_CR_STRT FLASH_CTL_START
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# define FLASH_CR_LOCK FLASH_CTL_LK
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# define FLASH_CR_PG FLASH_CTL_PG
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# define KEYR KEY
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#endif
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/* Serial USART redefines. */
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#if HAL_USE_SERIAL
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# if !defined(SERIAL_USART_CR1)
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# define SERIAL_USART_CR1 (USART_CTL0_PCEN | USART_CTL0_PM | USART_CTL0_WL) // parity enable, odd parity, 9 bit length
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# endif
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# if !defined(SERIAL_USART_CR2)
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# define SERIAL_USART_CR2 (USART_CTL1_STB_1) // 2 stop bits
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# endif
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# if !defined(SERIAL_USART_CR3)
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# define SERIAL_USART_CR3 0x0
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# endif
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# define USART_CR3_HDSEL USART_CTL2_HDEN
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# define CCR CHCV
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#endif
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/* SPI redefines. */
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#if HAL_USE_SPI
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# define SPI_CR1_LSBFIRST SPI_CTL0_LF
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# define SPI_CR1_CPHA SPI_CTL0_CKPH
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# define SPI_CR1_CPOL SPI_CTL0_CKPL
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# define SPI_CR1_BR_0 SPI_CTL0_PSC_0
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# define SPI_CR1_BR_1 SPI_CTL0_PSC_1
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# define SPI_CR1_BR_2 SPI_CTL0_PSC_2
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#endif
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