407 lines
11 KiB
C
407 lines
11 KiB
C
/* Copyright 2018 ishtob
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* Driver for DRV2605L written for QMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <stdint.h>
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/* Initialization settings
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* Feedback Control Settings */
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#ifndef FB_ERM_LRA
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# define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
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#endif
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#ifndef FB_BRAKEFACTOR
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# define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
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#endif
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#ifndef FB_LOOPGAIN
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# define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
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#endif
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/* LRA specific settings */
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#if FB_ERM_LRA == 1
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# ifndef V_RMS
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# define V_RMS 2.0
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# endif
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# ifndef V_PEAK
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# define V_PEAK 2.1
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# endif
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# ifndef F_LRA
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# define F_LRA 205
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# endif
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# ifndef RATED_VOLTAGE
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# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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# endif
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#endif
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#ifndef RATED_VOLTAGE
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# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
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#endif
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#ifndef V_PEAK
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# define V_PEAK 2.8
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#endif
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/* Library Selection */
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#ifndef DRV2605L_LIBRARY
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# if FB_ERM_LRA == 1
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# define DRV2605L_LIBRARY 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
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# else
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# define DRV2605L_LIBRARY 1
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# endif
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#endif
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#ifndef DRV2605L_GREETING
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# define DRV2605L_GREETING alert_750ms
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#endif
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#ifndef DRV2605L_DEFAULT_MODE
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# define DRV2605L_DEFAULT_MODE strong_click1
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#endif
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/* Control 1 register settings */
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#ifndef DRIVE_TIME
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# define DRIVE_TIME 25
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#endif
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#ifndef AC_COUPLE
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# define AC_COUPLE 0
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#endif
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#ifndef STARTUP_BOOST
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# define STARTUP_BOOST 1
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#endif
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/* Control 2 Settings */
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#ifndef BIDIR_INPUT
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# define BIDIR_INPUT 1
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#endif
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#ifndef BRAKE_STAB
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# define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
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#endif
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#ifndef SAMPLE_TIME
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# define SAMPLE_TIME 3
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#endif
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#ifndef BLANKING_TIME
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# define BLANKING_TIME 1
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#endif
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#ifndef IDISS_TIME
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# define IDISS_TIME 1
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#endif
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/* Control 3 settings */
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#ifndef NG_THRESH
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# define NG_THRESH 2
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#endif
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#ifndef ERM_OPEN_LOOP
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# define ERM_OPEN_LOOP 1
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#endif
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#ifndef SUPPLY_COMP_DIS
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# define SUPPLY_COMP_DIS 0
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#endif
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#ifndef DATA_FORMAT_RTO
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# define DATA_FORMAT_RTO 0
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#endif
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#ifndef LRA_DRIVE_MODE
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# define LRA_DRIVE_MODE 0
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#endif
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#ifndef N_PWM_ANALOG
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# define N_PWM_ANALOG 0
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#endif
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#ifndef LRA_OPEN_LOOP
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# define LRA_OPEN_LOOP 0
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#endif
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/* Control 4 settings */
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#ifndef ZC_DET_TIME
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# define ZC_DET_TIME 0
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#endif
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#ifndef AUTO_CAL_TIME
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# define AUTO_CAL_TIME 3
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#endif
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#define DRV2605L_I2C_ADDRESS 0x5A
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#define DRV2605L_REG_STATUS 0x00
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#define DRV2605L_REG_MODE 0x01
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#define DRV2605L_REG_RTP_INPUT 0x02
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#define DRV2605L_REG_LIBRARY_SELECTION 0x03
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_1 0x04
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_2 0x05
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_3 0x06
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_4 0x07
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_5 0x08
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_6 0x09
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_7 0x0A
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#define DRV2605L_REG_WAVEFORM_SEQUENCER_8 0x0B
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#define DRV2605L_REG_GO 0x0C
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#define DRV2605L_REG_OVERDRIVE_TIME_OFFSET 0x0D
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#define DRV2605L_REG_SUSTAIN_TIME_OFFSET_P 0x0E
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#define DRV2605L_REG_SUSTAIN_TIME_OFFSET_N 0x0F
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#define DRV2605L_REG_BRAKE_TIME_OFFSET 0x10
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#define DRV2605L_REG_AUDIO_TO_VIBE_CTRL 0x11
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#define DRV2605L_REG_AUDIO_TO_VIBE_MIN_INPUT 0x12
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#define DRV2605L_REG_AUDIO_TO_VIBE_MAX_INPUT 0x13
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#define DRV2605L_REG_AUDIO_TO_VIBE_MIN_OUTPUT_DRIVE 0x14
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#define DRV2605L_REG_AUDIO_TO_VIBE_MAX_OUTPUT_DRIVE 0x15
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#define DRV2605L_REG_RATED_VOLTAGE 0x16
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#define DRV2605L_REG_OVERDRIVE_CLAMP_VOLTAGE 0x17
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#define DRV2605L_REG_AUTO_CALIBRATION_COMPENSATION_RESULT 0x18
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#define DRV2605L_REG_AUTO_CALIBRATION_BACK_EMF_RESULT 0x19
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#define DRV2605L_REG_FEEDBACK_CTRL 0x1A
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#define DRV2605L_REG_CTRL1 0x1B
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#define DRV2605L_REG_CTRL2 0x1C
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#define DRV2605L_REG_CTRL3 0x1D
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#define DRV2605L_REG_CTRL4 0x1E
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#define DRV2605L_REG_CTRL5 0x1F
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#define DRV2605L_REG_LRA_OPEN_LOOP_PERIOD 0x20
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#define DRV2605L_REG_VBAT_VOLTAGE_MONITOR 0x21
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#define DRV2605L_REG_LRA_RESONANCE_PERIOD 0x22
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void drv2605l_init(void);
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void drv2605l_write(const uint8_t reg_addr, const uint8_t data);
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uint8_t drv2605l_read(const uint8_t reg_addr);
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void drv2605l_rtp_init(void);
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void drv2605l_amplitude(const uint8_t amplitude);
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void drv2605l_pulse(const uint8_t sequence);
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typedef enum DRV_EFFECT {
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clear_sequence,
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strong_click,
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strong_click_60,
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strong_click_30,
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sharp_click,
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sharp_click_60,
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sharp_click_30,
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soft_bump,
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soft_bump_60,
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soft_bump_30,
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dbl_click,
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dbl_click_60,
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trp_click,
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soft_fuzz,
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strong_buzz,
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alert_750ms,
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alert_1000ms,
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strong_click1,
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strong_click2_80,
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strong_click3_60,
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strong_click4_30,
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medium_click1,
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medium_click2_80,
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medium_click3_60,
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sharp_tick1,
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sharp_tick2_80,
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sharp_tick3_60,
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sh_dblclick_str,
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sh_dblclick_str_80,
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sh_dblclick_str_60,
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sh_dblclick_str_30,
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sh_dblclick_med,
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sh_dblclick_med_80,
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sh_dblclick_med_60,
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sh_dblsharp_tick,
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sh_dblsharp_tick_80,
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sh_dblsharp_tick_60,
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lg_dblclick_str,
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lg_dblclick_str_80,
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lg_dblclick_str_60,
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lg_dblclick_str_30,
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lg_dblclick_med,
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lg_dblclick_med_80,
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lg_dblclick_med_60,
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lg_dblsharp_tick,
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lg_dblsharp_tick_80,
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lg_dblsharp_tick_60,
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buzz,
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buzz_80,
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buzz_60,
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buzz_40,
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buzz_20,
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pulsing_strong,
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pulsing_strong_80,
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pulsing_medium,
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pulsing_medium_80,
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pulsing_sharp,
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pulsing_sharp_80,
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transition_click,
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transition_click_80,
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transition_click_60,
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transition_click_40,
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transition_click_20,
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transition_click_10,
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transition_hum,
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transition_hum_80,
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transition_hum_60,
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transition_hum_40,
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transition_hum_20,
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transition_hum_10,
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transition_rampdown_long_smooth1,
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transition_rampdown_long_smooth2,
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transition_rampdown_med_smooth1,
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transition_rampdown_med_smooth2,
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transition_rampdown_short_smooth1,
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transition_rampdown_short_smooth2,
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transition_rampdown_long_sharp1,
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transition_rampdown_long_sharp2,
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transition_rampdown_med_sharp1,
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transition_rampdown_med_sharp2,
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transition_rampdown_short_sharp1,
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transition_rampdown_short_sharp2,
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transition_rampup_long_smooth1,
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transition_rampup_long_smooth2,
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transition_rampup_med_smooth1,
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transition_rampup_med_smooth2,
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transition_rampup_short_smooth1,
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transition_rampup_short_smooth2,
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transition_rampup_long_sharp1,
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transition_rampup_long_sharp2,
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transition_rampup_med_sharp1,
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transition_rampup_med_sharp2,
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transition_rampup_short_sharp1,
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transition_rampup_short_sharp2,
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transition_rampdown_long_smooth1_50,
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transition_rampdown_long_smooth2_50,
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transition_rampdown_med_smooth1_50,
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transition_rampdown_med_smooth2_50,
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transition_rampdown_short_smooth1_50,
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transition_rampdown_short_smooth2_50,
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transition_rampdown_long_sharp1_50,
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transition_rampdown_long_sharp2_50,
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transition_rampdown_med_sharp1_50,
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transition_rampdown_med_sharp2_50,
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transition_rampdown_short_sharp1_50,
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transition_rampdown_short_sharp2_50,
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transition_rampup_long_smooth1_50,
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transition_rampup_long_smooth2_50,
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transition_rampup_med_smooth1_50,
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transition_rampup_med_smooth2_50,
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transition_rampup_short_smooth1_50,
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transition_rampup_short_smooth2_50,
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transition_rampup_long_sharp1_50,
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transition_rampup_long_sharp2_50,
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transition_rampup_med_sharp1_50,
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transition_rampup_med_sharp2_50,
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transition_rampup_short_sharp1_50,
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transition_rampup_short_sharp2_50,
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long_buzz_for_programmatic_stopping,
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smooth_hum1_50,
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smooth_hum2_40,
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smooth_hum3_30,
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smooth_hum4_20,
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smooth_hum5_10,
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drv_effect_max
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} DRV_EFFECT;
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/* Register bit array unions */
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typedef union DRVREG_STATUS { /* register 0x00 */
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uint8_t Byte;
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struct {
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uint8_t OC_DETECT : 1; /* set to 1 when overcurrent event is detected */
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uint8_t OVER_TEMP : 1; /* set to 1 when device exceeds temp threshold */
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uint8_t FB_STS : 1; /* set to 1 when feedback controller has timed out */
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/* auto-calibration routine and diagnostic result
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* result | auto-calibation | diagnostic |
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* 0 | passed | actuator func normal |
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* 1 | failed | actuator func fault* |
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* * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
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uint8_t DIAG_RESULT : 1;
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uint8_t : 1;
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uint8_t DEVICE_ID : 3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */
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} Bits;
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} DRVREG_STATUS;
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typedef union DRVREG_MODE { /* register 0x01 */
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uint8_t Byte;
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struct {
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uint8_t MODE : 3; /* Mode setting */
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uint8_t : 3;
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uint8_t STANDBY : 1; /* 0:standby 1:ready */
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} Bits;
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} DRVREG_MODE;
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typedef union DRVREG_WAIT {
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uint8_t Byte;
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struct {
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uint8_t WAIT_MODE : 1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
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uint8_t WAIT_TIME : 7;
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} Bits;
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} DRVREG_WAIT;
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typedef union DRVREG_FBR { /* register 0x1A */
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uint8_t Byte;
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struct {
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uint8_t BEMF_GAIN : 2;
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uint8_t LOOP_GAIN : 2;
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uint8_t BRAKE_FACTOR : 3;
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uint8_t ERM_LRA : 1;
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} Bits;
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} DRVREG_FBR;
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typedef union DRVREG_CTRL1 { /* register 0x1B */
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uint8_t Byte;
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struct {
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uint8_t C1_DRIVE_TIME : 5;
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uint8_t C1_AC_COUPLE : 1;
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uint8_t : 1;
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uint8_t C1_STARTUP_BOOST : 1;
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} Bits;
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} DRVREG_CTRL1;
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typedef union DRVREG_CTRL2 { /* register 0x1C */
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uint8_t Byte;
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struct {
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uint8_t C2_IDISS_TIME : 2;
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uint8_t C2_BLANKING_TIME : 2;
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uint8_t C2_SAMPLE_TIME : 2;
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uint8_t C2_BRAKE_STAB : 1;
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uint8_t C2_BIDIR_INPUT : 1;
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} Bits;
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} DRVREG_CTRL2;
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typedef union DRVREG_CTRL3 { /* register 0x1D */
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uint8_t Byte;
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struct {
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uint8_t C3_LRA_OPEN_LOOP : 1;
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uint8_t C3_N_PWM_ANALOG : 1;
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uint8_t C3_LRA_DRIVE_MODE : 1;
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uint8_t C3_DATA_FORMAT_RTO : 1;
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uint8_t C3_SUPPLY_COMP_DIS : 1;
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uint8_t C3_ERM_OPEN_LOOP : 1;
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uint8_t C3_NG_THRESH : 2;
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} Bits;
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} DRVREG_CTRL3;
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typedef union DRVREG_CTRL4 { /* register 0x1E */
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uint8_t Byte;
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struct {
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uint8_t C4_OTP_PROGRAM : 1;
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uint8_t : 1;
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uint8_t C4_OTP_STATUS : 1;
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uint8_t : 1;
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uint8_t C4_AUTO_CAL_TIME : 2;
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uint8_t C4_ZC_DET_TIME : 2;
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} Bits;
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} DRVREG_CTRL4;
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typedef union DRVREG_CTRL5 { /* register 0x1F */
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uint8_t Byte;
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struct {
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uint8_t C5_IDISS_TIME : 2;
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uint8_t C5_BLANKING_TIME : 2;
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uint8_t C5_PLAYBACK_INTERVAL : 1;
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uint8_t C5_LRA_AUTO_OPEN_LOOP : 1;
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uint8_t C5_AUTO_OL_CNT : 2;
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} Bits;
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} DRVREG_CTRL5;
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