8e614250b4
Co-authored-by: Pablo Martínez <58857054+elpekenin@users.noreply.github.com> Co-authored-by: Dasky <32983009+daskygit@users.noreply.github.com> Fixup delta frame coordinates after #20296.
157 lines
8.1 KiB
C
157 lines
8.1 KiB
C
// Copyright 2021 Paul Cotter (@gr1mr3aver)
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// Copyright 2023 Nick Brassel (@tzarc)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "qp_internal.h"
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#include "qp_comms.h"
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#include "qp_gc9a01.h"
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#include "qp_gc9a01_opcodes.h"
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#include "qp_tft_panel.h"
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Driver storage
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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tft_panel_dc_reset_painter_device_t gc9a01_drivers[GC9A01_NUM_DEVICES] = {0};
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Initialization
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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__attribute__((weak)) bool qp_gc9a01_init(painter_device_t device, painter_rotation_t rotation) {
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// A lot of these "unknown" opcodes are sourced from other OSS projects and are seemingly required for this display to function.
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// clang-format off
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const uint8_t gc9a01_init_sequence[] = {
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// Command, Delay, N, Data[N]
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GC9A01_SET_INTER_REG_ENABLE2, 0, 0,
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0xEB, 0, 1, 0x14,
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GC9A01_SET_INTER_REG_ENABLE1, 0, 0,
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GC9A01_SET_INTER_REG_ENABLE2, 0, 0,
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0xEB, 0, 1, 0x14,
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0x84, 0, 1, 0x40,
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0x85, 0, 1, 0xFF,
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0x86, 0, 1, 0xFF,
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0x87, 0, 1, 0xFF,
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0x88, 0, 1, 0x0A,
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0x89, 0, 1, 0x21,
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0x8a, 0, 1, 0x00,
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0x8b, 0, 1, 0x80,
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0x8c, 0, 1, 0x01,
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0x8d, 0, 1, 0x01,
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0x8e, 0, 1, 0xFF,
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0x8f, 0, 1, 0xFF,
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GC9A01_SET_FUNCTION_CTL, 0, 2, 0x00, 0x20,
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GC9A01_SET_PIX_FMT, 0, 1, 0x55,
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0x90, 0, 4, 0x08, 0x08, 0x08, 0x08,
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0xBD, 0, 1, 0x06,
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0xBC, 0, 1, 0x00,
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0xFF, 0, 3, 0x60, 0x01, 0x04,
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GC9A01_SET_POWER_CTL_2, 0, 1, 0x13,
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GC9A01_SET_POWER_CTL_3, 0, 1, 0x13,
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GC9A01_SET_POWER_CTL_4, 0, 1, 0x22,
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0xBE, 0, 1, 0x11,
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0xE1, 0, 2, 0x10, 0x0E,
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0xDF, 0, 3, 0x21, 0x0C, 0x02,
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GC9A01_SET_GAMMA1, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A,
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GC9A01_SET_GAMMA2, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F,
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GC9A01_SET_GAMMA3, 0, 6, 0x45, 0x09, 0x08, 0x08, 0x26, 0x2A,
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GC9A01_SET_GAMMA4, 0, 6, 0x43, 0x70, 0x72, 0x36, 0x37, 0x6F,
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0xED, 0, 2, 0x1B, 0x0B,
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0xAE, 0, 1, 0x77,
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0xCD, 0, 1, 0x63,
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0x70, 0, 9, 0x07, 0x07, 0x04, 0x0E, 0x0F, 0x09, 0x07, 0x08, 0x03,
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GC9A01_SET_FRAME_RATE, 0, 1, 0x34,
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0x62, 0, 12, 0x18, 0x0D, 0x71, 0xED, 0x70, 0x70, 0x18, 0x0F, 0x71, 0xEF, 0x70, 0x70,
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0x63, 0, 12, 0x18, 0x11, 0x71, 0xF1, 0x70, 0x70, 0x18, 0x13, 0x71, 0xF3, 0x70, 0x70,
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0x64, 0, 7, 0x28, 0x29, 0xF1, 0x01, 0xF1, 0x00, 0x07,
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0x66, 0, 10, 0x3C, 0x00, 0xCD, 0x67, 0x45, 0x45, 0x10, 0x00, 0x00, 0x00,
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0x67, 0, 10, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0x54, 0x10, 0x32, 0x98,
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0x74, 0, 7, 0x10, 0x85, 0x80, 0x00, 0x00, 0x4E, 0x00,
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0x98, 0, 2, 0x3E, 0x07,
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GC9A01_CMD_TEARING_OFF, 0, 0,
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GC9A01_CMD_INVERT_OFF, 0, 0,
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GC9A01_CMD_SLEEP_OFF, 120, 0,
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GC9A01_CMD_DISPLAY_ON, 20, 0
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};
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// clang-format on
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// clang-format on
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qp_comms_bulk_command_sequence(device, gc9a01_init_sequence, sizeof(gc9a01_init_sequence));
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// Configure the rotation (i.e. the ordering and direction of memory writes in GRAM)
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const uint8_t madctl[] = {
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[QP_ROTATION_0] = GC9A01_MADCTL_BGR,
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[QP_ROTATION_90] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MV,
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[QP_ROTATION_180] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MX | GC9A01_MADCTL_MY,
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[QP_ROTATION_270] = GC9A01_MADCTL_BGR | GC9A01_MADCTL_MV | GC9A01_MADCTL_MY,
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};
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qp_comms_command_databyte(device, GC9A01_SET_MEM_ACS_CTL, madctl[rotation]);
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return true;
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Driver vtable
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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const tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = {
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.base =
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{
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.init = qp_gc9a01_init,
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.power = qp_tft_panel_power,
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.clear = qp_tft_panel_clear,
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.flush = qp_tft_panel_flush,
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.pixdata = qp_tft_panel_pixdata,
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.viewport = qp_tft_panel_viewport,
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.palette_convert = qp_tft_panel_palette_convert_rgb565_swapped,
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.append_pixels = qp_tft_panel_append_pixels_rgb565,
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.append_pixdata = qp_tft_panel_append_pixdata,
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},
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.num_window_bytes = 2,
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.swap_window_coords = false,
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.opcodes =
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{
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.display_on = GC9A01_CMD_DISPLAY_ON,
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.display_off = GC9A01_CMD_DISPLAY_OFF,
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.set_column_address = GC9A01_SET_COL_ADDR,
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.set_row_address = GC9A01_SET_PAGE_ADDR,
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.enable_writes = GC9A01_SET_MEM,
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},
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};
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#ifdef QUANTUM_PAINTER_GC9A01_SPI_ENABLE
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// Factory function for creating a handle to the ILI9341 device
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painter_device_t qp_gc9a01_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode) {
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for (uint32_t i = 0; i < GC9A01_NUM_DEVICES; ++i) {
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tft_panel_dc_reset_painter_device_t *driver = &gc9a01_drivers[i];
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if (!driver->base.driver_vtable) {
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driver->base.driver_vtable = (const painter_driver_vtable_t *)&gc9a01_driver_vtable;
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driver->base.comms_vtable = (const painter_comms_vtable_t *)&spi_comms_with_dc_vtable;
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driver->base.native_bits_per_pixel = 16; // RGB565
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driver->base.panel_width = panel_width;
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driver->base.panel_height = panel_height;
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driver->base.rotation = QP_ROTATION_0;
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driver->base.offset_x = 0;
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driver->base.offset_y = 0;
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// SPI and other pin configuration
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driver->base.comms_config = &driver->spi_dc_reset_config;
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driver->spi_dc_reset_config.spi_config.chip_select_pin = chip_select_pin;
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driver->spi_dc_reset_config.spi_config.divisor = spi_divisor;
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driver->spi_dc_reset_config.spi_config.lsb_first = false;
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driver->spi_dc_reset_config.spi_config.mode = spi_mode;
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driver->spi_dc_reset_config.dc_pin = dc_pin;
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driver->spi_dc_reset_config.reset_pin = reset_pin;
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driver->spi_dc_reset_config.command_params_uses_command_pin = false;
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if (!qp_internal_register_device((painter_device_t)driver)) {
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memset(driver, 0, sizeof(tft_panel_dc_reset_painter_device_t));
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return NULL;
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}
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return (painter_device_t)driver;
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}
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}
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return NULL;
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}
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#endif // QUANTUM_PAINTER_GC9A01_SPI_ENABLE
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