Implement detection of new CPU features: AVX2 and BMI2
This commit is contained in:
parent
2edd12fe22
commit
15b6c7d3b7
|
@ -189,7 +189,7 @@ static int TrySSE2()
|
|||
|
||||
int g_x86DetectionDone = 0;
|
||||
int g_hasISSE = 0, g_hasSSE2 = 0, g_hasSSSE3 = 0, g_hasMMX = 0, g_hasAESNI = 0, g_hasCLMUL = 0, g_isP4 = 0;
|
||||
int g_hasAVX = 0, g_hasSSE42 = 0, g_hasSSE41 = 0;
|
||||
int g_hasAVX = 0, g_hasAVX2 = 0, g_hasBMI2 = 0, g_hasSSE42 = 0, g_hasSSE41 = 0;
|
||||
uint32 g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
|
||||
|
||||
VC_INLINE int IsIntel(const uint32 output[4])
|
||||
|
@ -292,6 +292,8 @@ void DetectX86Features()
|
|||
g_hasMMX = (cpuid1[3] & (1 << 23)) != 0;
|
||||
if ((cpuid1[3] & (1 << 26)) != 0)
|
||||
g_hasSSE2 = TrySSE2();
|
||||
g_hasAVX2 = g_hasSSE2 && (cpuid1[1] & (1 << 5));
|
||||
g_hasBMI2 = g_hasSSE2 && (cpuid1[1] & (1 << 8));
|
||||
g_hasAVX = g_hasSSE2 && (cpuid1[2] & (1 << 28));
|
||||
g_hasSSE42 = g_hasSSE2 && (cpuid1[2] & (1 << 20));
|
||||
g_hasSSE41 = g_hasSSE2 && (cpuid1[2] & (1 << 19));
|
||||
|
|
|
@ -167,6 +167,8 @@ extern "C" {
|
|||
// these should not be used directly
|
||||
extern int g_x86DetectionDone;
|
||||
extern int g_hasAVX;
|
||||
extern int g_hasAVX2;
|
||||
extern int g_hasBMI2;
|
||||
extern int g_hasSSE42;
|
||||
extern int g_hasSSE41;
|
||||
extern int g_hasSSSE3;
|
||||
|
@ -196,6 +198,8 @@ extern int g_hasMMX;
|
|||
#define HasSSE42() g_hasSSE42
|
||||
#define HasSSE41() g_hasSSE41
|
||||
#define HasSAVX() g_hasAVX
|
||||
#define HasSAVX2() g_hasAVX2
|
||||
#define HasSBMI2() g_hasBMI2
|
||||
#define HasSSSE3() g_hasSSSE3
|
||||
#define HasAESNI() g_hasAESNI
|
||||
#define HasCLMUL() g_hasCLMUL
|
||||
|
|
Loading…
Reference in New Issue